A dual data rate (DDR) memory is characterized by a data signal that provides bits of information during the rising edge of a clock signal as well as the falling edge of the DQS signal. Accordingly, 2 bits/cycle are possible. The data signal is to be sampled at 90 and 270 degrees phase shift from the DQS signal.
As the clock signal increases, such as from 100 MHz to 200 MHz, the time period shrinks from 10 ns to 5 ns. Skews that may be permissible for slower clocks become unacceptable for faster clocks.
Integrated circuits are generally designed using synthesis tools. The timing for data pins in a DDR memory are carefully measured and adjusted. However, as the number of data pins increases, the effort is also repeated. This leads to increased prefabrication period.
Further limitations and disadvantages of conventional and traditional systems will become apparent to one of skill in the art through comparison of such systems with the invention as set forth in the remainder of the present application with reference to the drawings.